Overview

Hardware Architectures

There are two different architectures for the RISC5 CPU and its environment:

• ETH: as defined and implemented by

  • Project Oberon (Niklaus Wirth, Jürg Gutknecht, Paul Reed)
  • Embedded Project Oberon (Chris Burrows)

• THM: as defined and implemented by

  • THM Oberon (Hellwig Geisse)

The main difference is the implementation of the RISC5 CPU, and its peripheral bus. The THM CPU version used is mostly¹ binary compatible with the ETH one and can be used with the Astrobe compiler. THM’s peripheral bus uses an explicit handshake (strobe and ack). However, the peripheral devices, such as RS232 or SPI, can (and are) designed to work with both architectures.

Refer to the repository for the list of Verilog modules that work on both architectures (any), or are specific to an architecture (eth, thm), or to an FPGA board.

Platforms

A platform is based on:

• a HW architecture
• a specific FPGA board
• an implementation of the RISC5 CPU on that FPGA, according to the architecture
• a defined set of peripherals and devices on that FPGA
• allocation of connections between the FPGA and the electronic devices and connectors on the board

consequently, a programming model, including

• a CPU and its instruction set (as of now, the RISC5 CPU)
• RAM and PROM memory map
• device IO memory map
• device functionality (IO devices and others on the FPGA)

Specifically, a platform is defined via its top Verilog module, a project file (Vivado or Quartus) to select a specific variant of each functional module, and a corresponding definition file for the board connections of the FPGA chip, depending on the FPGA used either an xdc (Xilinx) or a qsf (Altera) file.

Defined Platforms (GitHub)

• Embedded Project Oberon
• Oberon RTS

FPGA Boards Used

• Digilent Arty A7-100 (Artix-7), short code “arty-a7-100”
• Terasic DE2-115 (Cyclone IV), short code “de2-115”
• Digilent Nexys Video (Artix-7), short code “nexys-a7-100”
• Terasic Cyclone V GX Starter Kit (Cyclone V), short code “cv-sk”