One RISC5 Interrupt
When coming from the world of “normal” microprocessors, interrupts are central to implement many real-time system features. A process writes to a buffer and yields control to allow other processes to run, while a corresponding interrupt handler empties the buffer sending data to a peripheral. That sort of thing.
The RISC5 processor provides one interrupt. The Cortex M3 has dozens. Each MCU device has one or more interrupts, each with a corresponding vector and interrupt handler. There are interrupts for hardware faults, and for exceptions such the system ticker and watchdogs. The interrupt handling machinery is complex, with priorities, enabling/disabling bits, different events per interrupt, nesting of interrupts, and so on. Powerful, flexible, but complex.
Interrupts or Silicon
Coming from the M3, I thought I should extend the single RISC5 interrupt by a software solution that allows to register different handlers, possibly from many modules, to be called upon different conditions when the one RISC5 interrupt is triggered.
The RISC5 interrupt clearly is not meant to be used in this way. For starters, the interrupt handler is not even assumed to call procedures – the link register is not saved upon entry into the handler.
While this can be solved in the handler itself, Paul Reed gently and kindly slapped my wrist, pointing out that with an FPGA at my disposal I should assume a different mindset: avoid interrupts if possible, and rather implement a solution in the FPGA – which extends the solution space from the software into the hardware. He’s right. Non-trivial interrupt setups can get cumbersome quickly, not least with an eye on the overall robustness of a system or program.
I have since assumed this proposed mindset, or at least tried to, for example:
Interrupt Controller
Now let’s assume a situation where the processor needs to react swiftly to actual external events in the controlled environment, eg. to capture a value or measurement, and an FPGA-based solution does not meet the requirements for whatever reason, but an interrupt-based one would. And we have two, or four, or eight external interrupt sources that need to be handled differently.
Here’s where the interrupt controller comes into play.