Embedded Oberon for Real-time Systems
Oberon RTS is experimental work in progress to adapt and extend Embedded Project Oberon for the use as real-time operating system for controllers.
Embedded Project Oberon (EPO) was created, and is maintained, by Chris Burrows of Astrobe fame. It’s a brilliant concept, and implementation thereof, to make the Oberon system and language available on commercially available target Xilinx FPGA boards implementing the Project Oberon RISC5 processor. The editing and compilation of Oberon modules is done on a Windows PC, while the board only runs a minimal core of the Oberon system, called Embedded Project Oberon. Astrobe for RISC5 provides a console, connected to the remote board via a serial link, to upload the compiled modules, plus a terminal to execute commands on the remote board.
Project Oberon (PO) was created by Niklaus Wirth, Jürg Gutknecht, and Paul Reed. Project Oberon comprises the Oberon language, the Oberon operating system, as well as the RISC5 processor, accompanied by a book describing the whole technology stack. The source code of all Oberon software as well as the Verilog design files are available, too, allowing to study and understand everything down to the bits and logic gates.
Embedded Project Oberon is directly based on Project Oberon, and it offers the same openness as regards availability of Oberon source code and Verilog design files. Check out Astrobe for RISC5. Chris makes this complete environment freely available. Amazing.
THM-Oberon is an alternative architecture and implementation of the RISC5 processor, created by Hellwig Geisse.
This site is targeted at programmers with a good understanding of Embedded Project Oberon, both with respect to the Oberon software as well as the FPGA hardware. At least for now, there are no Getting Started instructions, and no tutorials. The modules in the GitHub repositories are provided “as is”, with the assumption that the reader knows how to compile the software and create the FPGA configuration files using the tools as outlined below.
This is explorative and experimental work, and Oberon modules, Verilog designs, as well as the texts and descriptions on this site might be incomplete, or out of date, and will be evolving.
Refer to the GitHub repos for the actual details. As the saying goes: “Debug only code, don’t get suckered in by the comments.” Or by websites.
The Oberon software is written for the Astrobe for RISC5 compiler. To configure the FPGA hardware via Verilog, either Vivado or Quartus is used for Xilinx or Altera FPGAs, respectively.
The menus at the top are drop-downs, where applicable, but you can also click on the menu name item itself to get an overview page. The item on the top left-hand side is the home link.
On narrow mobile phone screens, the main menu itself is a drop-down, with no secondary drop-down from there. This would be awkward. Navigate via the overview pages in this case.