RISC5 for Embedded Oberon

Design Files

The RISC5 processor for Embedded Oberon is both a subset of the processor defined and described in the book Project Oberon by Niklaus Wirth and Jürg Gutknecht, as well as an extension thereof.

The Astrobe distribution comprises these Verilog files:

  • RISC5Top.v
  • RISC5.v
  • Registers.v
  • Divider.v, Multiplier.v
  • FPAdder.c, FPDivider.v, FPMultiplier.v
  • LeftShifter.v, RightShifter.v
  • PROM.c, RAM.v
  • I2C.v
  • RS232R.v, RS232T.v
  • SPI.v

Plus a constraints file, eg. ArtyA7.xdc, that mostly serves to allocate the FPGA IO pins to the IO lines of the RISC5 processor, as defined in RISC5Top.v. Due to the different FPGAs used and the physical layout of the boards, this constraints file is board-specific.

In the above list, only RISC5Top.v and RAM.v are board-specific, to implement different RAM sizes within the limits of the corresponding FPGA chip.

Programming the FPGA

Refer to the documentation for Astrobe for RISC5 to learn how to set up a working processor for Embedded Oberon.

Making Changes

Simple rule: don’t change anything of RISC5 that the Oberon Inner Core refers to, as you cannot – and should not – make changes to the modules of the Inner Core.

These elements are hard-coded in the Inner Core:

  • certain device IO addresses, in particular SPI
  • SPI status register bits

The SPI device is critical in this context, as without it working properly, the system will not even boot.

As special case, the device address of the LEDs is also fixed, but in the compiler.

Having said that, it’s possible to make changes in the IO address space, but the hard-coded addresses must be preserved. The Oberon code refers to these addresses via negative numbers, which results in some useable leeway.