This section introduces explorative specific designs, consisting of Oberon and Verilog modules. The descriptions only present parts of modules, to cover the basic idea and implementation. These code snippets could be out of sync with the sources on GitHub (when they become accessible, see next point). Also, newer designs might make changes that are not fully compatible any more with former ones.
The plan is to transfer these designs, or a subset thereof, into the “final” structure and design of Oberon RTS. See the system description.
The links to the sources on GitHub are still missing. Sorry about that.