Notes about this section.
An FPGA-based timer per process.
Global fixed timing schedule for all processes.
Adding process priorities.
Adding process priorities, more lightweight.
Non-blocking IO with cooperative device interaction.
Recovering from run-time errors, and catching more errors.
Loading modules on system startup.
Minimising the really required modules.
Representing FPGA-based devices in Oberon modules.
SPI Device with extended control features.
Adding a few buffers to the Extended SPI device.
Extending the RISC5 interrupt capabilities.
Interrupting faulty task handlers.
Basis for inter-CPU communication.
Executing commands on “the other” CPU.
Breaking up the central system module.
Task based control processes.
The current scheduling approach in Tasks.Loop
Dynamically tracking the stack use in the FPGA.